1. Field of the Invention
The present invention relates generally to semiconductor devices and methods of forming semiconductor devices, and more particularly to methods of forming semiconductor devices having field oxides in trenches.
2. Description of the Related Art
Field oxides in a semiconductor device are used to isolate devices from neighboring devices. As semiconductor devices become highly integrated, field oxides occupying small areas and having superior insulation characteristics are required.
Field oxides can be formed by using a shallow trench isolation (STI) method or by using a local oxidation of silicon (LOCOS) method. According to the STI method, a semiconductor substrate is etched to form a trench having a predetermined depth, and the trench is filled with insulation layers. The STI method can form field oxides occupying small areas and having a superior insulation characteristics in comparison with a local oxidation of silicon (LOCOS) method of forming a thermal oxide at a semiconductor substrate.
Semiconductor devices may be classified into volatile memory devices and a nonvolatile memory devices. A volatile memory device is a memory device which will lose data stored in a memory cell when the power supply is cut down. A non-volatile memory device is a device which will retain data stored in a memory cell even though the power supply is cut down. Volatile memory device include dynamic random access memory (DRAM) devices and a static random access memory (SRAM) devices. A flash memory device is a nonvolatile memory device.
Generally, when data is stored in a memory cell of a flash memory device or erased there from, a higher operation voltage is needed. Thus, in general flash memory devices have a high-voltage region where devices are formed so as to control high voltages.
FIGS. 1 and 2 illustrate by cross-sectional views a conventional method of forming a flash memory device having field oxides. In the FIGS. 1 and 2, reference letters “a” and “b” indicate a cell region and a high-voltage region, respectively.
Referring to FIGS. 1 and 2, a semiconductor substrate 1 having the cell region “a” and the high-voltage region “b” is prepared. A channel stop impurity-doped region 2 is formed into the semiconductor substrate 1 of the high-voltage region “b” with a predetermined depth. A hard mask layer 3 is formed on a surface of the semiconductor substrate 1 having the channel stop impurity-doped region 2. The hard mask layer 3 is patterned to form a cell trench 4a to define an active region at the cell region “a” and to simultaneously form a high-voltage trench 4b exposing the channel stop impurity-doped region 2 at the high-voltage region “b”. A higher voltage than a power voltage is supplied on the high-voltage region “b”. As the high-voltage trench 4b has a deeper depth and a wider width. The cell trench 4a and the high-voltage trench 4b are simultaneously formed. Thus, the cell trench 4a and the high-voltage trench 4b have the same depth. Furthermore, the cell trench 4a has a narrower width than the high-voltage trench 4b. As a result, an aspect ratio of the cell trench 4a is higher than the high-voltage trench 4b. 
A field oxide layer 5 is formed on a surface of a semiconductor substrate 1 to fill the cell trench 4a and the high-voltage trench 4b. 
The field oxide layer 5 is planarized to expose the hard mask layer 3 and to form a cell field oxide 5a filling the cell trench 4a and a high-voltage field oxide 5b filling the high-voltage trench 4b. A high-voltage gate pattern (not illustrated) is formed at the high-voltage region “b”, and an impurity-doped region 7 is formed into an active region at both sides of the high-voltage gate pattern. The impurity-doped region 7 corresponds to source/drain regions of a high-voltage transistor.
In the described conventional method, voids 6 may be formed in the cell field oxides 5a due to the high aspect ratio of the cell trenches 4a. The voids 6 may deteriorate reliability of a semiconductor device.
The voids 6 may be prevented by reducing the depth of the cell trench 4a. In this case, however, the depth of the high-voltage trench 4b is also reduced. As a result, a punch through may occur between the source/drain regions 7 for the high-voltage transistor at the both side walls of the high-voltage filed oxide 5b. Additionally, as the channel stop impurity-doped region 2 is close to the surface of the active region at the high-voltage region b, a channel region (not illustrated) under the high-voltage transistor has a high-doping concentration to increase a threshold voltage of the high-voltage transistor. This can result in reliability problems of the high-voltage transistor.